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78M6610+PSU Data Sheet
4.3
I 2 C Interface
The 78M6610+PSU has an I C interface available at the SDAI, SDAO, and SCL pins. The interface
supports I C slave mode with a 7-bit address and operates at a data rate up to 400 kHz. Figure 19 shows
2
2
two possible configurations. Configuration A is the standard configuration. The double pin for SDA allows
the isolated configuration B.
V 3P3 or 5VDC
5VDC
SDAi
V 3P3 or 5VDC
SDA
SDAi
SDAo
SDA
V 3P3 or 5VDC
SDAo
I2C_GND
SCK
SCK
SCK
5VDC
SCK
A) STANDARD CONFIGURATION
B) ISOLATED CONFIGURATION
Figure 19: I C Bus Connection in Standard (A) and Isolated (B) Configuration
The I C interface allows access to read and write registers contained in a 256 word (24-bit) area of the
relevant address for the I C access. While access to a single byte is possible, it is highly recommended
2
2
on-chip RAM. The address of each register specified in Section 3 must be divided by 3 to obtain the
2
that the user access words (or multiple words) of data with each transaction.
The device address of each 78M6610+PSU is configured through the register DevAddr, which defines
address bits 6 through 2 of the device address. Address bits 0 and 1 are configured through pins ADDR1
and SPCK/ADDR0 (24-pin package). With the 16-pin package option, the DevAddr register defines
address bits 6 though 1, while bit 0 is configured through the pin SPCK/ADDR0.
Rev 1
49
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